1. Field of the Invention
The present invention relates generally to a system including a number of data driven information processors, and more specifically, to a method of verifying whether or not identification data in each processor included in such a system is preset to a correct value.
2. Description of the Related Art
In a data driven processor, processings proceed in parallel based on the simple rule "when all the data needed for an action are available and necessary resources such as an operation unit for the action are allocated for the action, the action is taken".
FIG. 1 is a block diagram showing a conventional data driven information processing system suitable for video processing. A similar system configuration is suggested in a document entitled "An Evaluation of Parallel Processing in the Dynamic Data Driven Processor" (issued in the Microcomputer Architecture Symposium sponsored by Information Processing Society of Japan, Nov. 12, 1991).
The system shown in FIG. 1 includes a data driven processor 1 and a video memory unit 11.
Video memory unit 11 includes a memory interface 2 and a video memory 3.
Processor 1 has input ports IA, IB and IV, and output ports OA, OB, and OV. Transmission paths 7 and 8 are connected to input ports IA and IB, respectively, and video signals to be processed are applied through transmission paths 7 and 8. A transmission path 5 is connected to input port IV, and a result of accessing to memory 3 in video memory unit 11 is applied through transmission path 5. Transmission paths 9 and 10 are connected to output ports OA and OB, respectively, and a result of processing by the system is output onto transmission paths 9 and 10. A transmission path 4 is connected to output port OV, and data for accessing video memory unit 11 is output onto transmission path 4. Memory interface 2 and video memory 3 are connected through a memory access control line 6. Note that a datapacket is transmitted through transmission paths 4 to 10.
In a data processing operation, a time-series of datapackets for signal input is applied to processor 1 through input port IA or IB, and each of the datapackets has a generation number allocated based on the order in which they are input. Processor 1, which prestores a data flow program for video processing, processes applied data based on the program. Processor 1 outputs a datapacket resulting from the processing through one of output ports OA, OB and OV. A datapacket sent out from processor 1 to video memory unit 11 through output port OV stores an access request (reference to/update of data stored in video memory 3).
Upon receiving such an access request, memory interface 2 accesses video memory 3 through memory access control line 6. Memory interface 2 applies a datapacket obtained as a result of the accessing to the input port IV of processor 1 through transmission path 5.
Processor 1 processes the datapacket applied through input port IV based on the program. Processor 1 outputs a datapacket obtained as a result of the processing at one of output ports OA, OB and OV.
Referring to FIG. 2, a datapacket applied to the video memory unit includes an instruction code (a), a generation number (b), data 1 (c) and data 2 (d) as well as a processor number (e) for uniquely specifying the data driven processor in the system which is determined to process the datapacket. These pieces of data are of 8 bits, 24 bits, 12 bits, 12 bits, and 10 bits in length. It should be noted that the field configuration and the bit length of each field are described simply by way of example.
Instruction code (a) is for specifying the content of a processing to video memory 3. Instruction code (a) specifies a read instruction instructing a process of reading data stored in the video memory or an update instruction instructing a process of updating data stored in video memory 3.
Generation number (b) is an identifier attached to a datapacket based on the order of input when the datapacket is input to data driven processor 1 through data transmission path 7 or 8. Generation number (b) is used for matching of datapackets in processor 1, and for addressing of video memory 3 in video memory unit 11.
Data 1 (c) and data 2 (d) are interpreted based on the content of instruction code (a). If instruction code (a) is an update instruction, data 1 (c) indicates data to be written into video memory 3, while data 2 (d) has no meaning. If instruction code (a) is a read instruction, data 1 (c) and data 2 (d) both have no meaning.
Referring to FIG. 3, a datapacket output from video memory unit 11 and a datapacket input/output to/from data driven processor 1 for video processing includes an instruction code (f), a generation number (g), data 1 (h), and a processor number (i). Their lengths are 8 bits, 24 bits, 12 bits, and 10 bits, respectively. Note that the field configuration and the bit length of each field are described simply by way of example.
If a datapacket as shown in FIG. 3 is output from video memory unit 11, instruction code (a), generation number (b) and processor number (e) shown in FIG. 2 are stored in the fields of instruction code (f), generation number (g), and processor number (i) shown in FIG. 3, respectively. Data obtained as a result of accessing video memory 3 based on instruction code (a) in FIG. 2 is stored in data 1 (h).
FIG. 4 illustrates a system configuration including four conventional data driven processors 1 for video processing. The four processors 1 in the system are allocated identification numbers PE#0, PE#1, PE#2, and PE#3, respectively for identifying one from another. Now, the structure and operation of the system shown in FIG. 4 will be described specifying a processor with an identification number.
In the system in FIG. 4, a network is established such that a datapacket can be provided to any arbitrary processor from any other processor. Assume that a datapacket will be provided from processor PE# to processor PE#1, for example. Processor PE# outputs a datapacket at output port OA and applies the output datapacket to the input port IA of processor PE#3. Processor PE#3 outputs the datapacket at output port OA. As a result, the datapacket is applied to the input port IA of processor PE#1.
FIG. 5 is a block diagram of the conventional data driven processor 1 suitable for video processing shown in FIGS. 1 and 4. Referring to FIG. 5, conventional processor 1 includes an input processing unit 17 having an input stage to which input port IA and IB are connected, a junction unit 12, a main body processing unit 13 for executing a processing based on a data flow program stored therein, a branching unit 14, an output processing unit 15 having an output stage to which output ports OA and OB are connected, and a PE# register 16 storing an identification number PE# unique to the processor 1 for identifying itself in the network of the system.
Input processing unit 17 receives a datapacket applied at input port IA or IB. Input processing unit 17 compares the processor number in the datapacket with the content of register 16. If they are in agreement, input processing unit 17 determines that the datapacket is destined thereto and outputs the datapacket to junction unit 12. Input processing unit 17 otherwise determines that the datapacket is destined to another processor and applies the datapacket to output processing unit 15.
Junction unit 12 merges datapackets applied from input processing unit 17 and datapackets applied from branching unit 14 for output to main body processing unit 13. Branching unit 14 will be described later.
Main body processing unit 13 processes the applied datapacket based on a prestored data flow program. During the processing, an access request to video memory 3 may occur. In such a case, main body processing unit 13 sends the packet under processing (see FIG. 2) through output port OV to video memory unit 11 and receives therefrom a packet obtained as a result of processing through input port IV (see FIG. 3).
Branching unit 14 receives a datapacket output from main body processing unit 13 and compares a processor number stored in the datapacket and the content of register 16 as input processing unit 17 does. Branching unit 14 applies the datapacket to junction unit 12 if they are in agreement, or else to output processing unit 15.
Output processing unit 15 receives datapackets applied from input processing unit 17 and branching unit 14. Output processing unit 15 selects one of output ports OA and OB based on a processor number stored in a datapacket and a preset branching condition. Output processing unit 15 outputs the datapacket at the selected output port.
While a processing based on a data flow program is in progress in the system as illustrated in FIG. 4, a processing result cannot be obtained as expected in some cases. In other words, the system may not sometimes operate as expected. In such a case the location of the fault responsible should be specified, the kind of fault should be specified, and countermeasure should be considered, in order to cope with the situation. This is however not easily done. Specifying the location of such a fault would be harder particularly if the number of processors included in the system is larger.
The above-described operation fault can be caused by an erroneous setting of PE# register in processor 1. If PE# register is erroneously set, a datapacket cannot be transferred correctly between processors.
Conventionally, for PE# register 16, hardware which provides processor 1 with prescribed terminal voltage or software including a special instruction for setting data in register 16 is used. If any of these setting methods is adopted, however, the conventional system does not have a function of verifying the content set in PE# register 16, and therefore the content of PE# register cannot be confirmed.